This invention relates to flash memory arrays and in particular to the structures of flash memory arrays and methods of forming them.
There are many commercially successful nonvolatile memory products being used today, particularly in the form of small form factor cards, which use an array of flash EEPROM (Electrically Erasable and Programmable Read Only Memory) cells. Such cards may be interfaced with a host, for example, by removably inserting a card into a card slot in a host. Some of the commercially available cards are CompactFlash™ (CF) cards, MultiMedia cards (MMC), Secure Digital (SD) cards, Smart Media cards, personnel tags (P-Tag) and Memory Stick cards. Hosts include personal computers, notebook computers, personal digital assistants (PDAs), various data communication devices, digital cameras, cellular telephones, portable audio players, automobile sound systems, and similar types of equipment. In an alternative arrangement to the separate card and host described above, in some examples a memory system is permanently connected to a host providing an embedded memory that is dedicated to the host.
Two general memory cell array architectures have found commercial application, NOR and NAND. In a typical NOR array, memory cells are connected between adjacent bit line source and drain diffusions that extend in a column direction with control gates connected to word lines extending along rows of cells. A memory cell includes at least one storage element positioned over at least a portion of the cell channel region between the source and drain. A programmed level of charge on the storage elements thus controls an operating characteristic of the cells, which can then be read by applying appropriate voltages to the addressed memory cells. Examples of such cells, their uses in memory systems and methods of manufacturing them are given in the following U.S. Pat. Nos. 5,070,032; 5,095,344; 5,313,421; 5,315,541; 5,343,063; 5,661,053 and 6,222,762. These patents, along with all other patents, patent applications and other publications referred to in this application are hereby incorporated by reference in their entirety for all purposes.
In a NAND array series strings of more than two memory cells, such as 16 or 32, are connected along with one or more select transistors between individual bit lines and a reference potential to form columns of cells. Word lines extend across cells within a large number of these columns. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be turned on hard so that the current flowing through a string is dependent upon the level of charge stored in the addressed cell. An example of a NAND architecture array and its operation as part of a memory system is found in the following U.S. Pat. Nos. 5,570,315; 5,774,397; 6,046,935 and 6,522,580. NAND memory devices have been found to be particularly suitable for mass storage applications such as those using removable memory cards.
The charge storage elements of current flash EEPROM arrays, as discussed in the foregoing referenced patents, are most commonly electrically conductive floating gates, typically formed from conductively doped polysilicon material. An alternate type of memory cell useful in flash EEPROM systems utilizes a non-conductive dielectric material in place of the conductive floating gate to store charge in a non-volatile manner. A triple layer dielectric formed of silicon dioxide, silicon nitride and silicon oxide (ONO) is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region, and erased by injecting hot holes into the nitride. Several specific cell structures and arrays employing dielectric storage elements are described in U.S. Pat. No. 6,925,007.
As in most integrated circuit applications, the pressure to shrink the silicon substrate area required to implement some integrated circuit function also exists with flash EEPROM systems. It is continually desired to increase the amount of digital data that can be stored in a given area of a silicon substrate, in order to increase the storage capacity of a given size memory card and other types of packages, or to both increase capacity and decrease size. One way to increase the storage density of data is to store more than one bit of data per memory cell. This is accomplished by dividing a window of a floating gate charge level voltage range into more than two states. The use of four such states allows each cell to store two bits of data, eight states stores three bits of data per cell, and so on. A multiple state flash EEPROM structure and operation is described in U.S. Pat. Nos. 5,043,940 and 5,172,338, which patents are incorporated herein by this reference.
Increased data density can also be achieved by reducing the physical size of the memory cells and/or the overall array. Shrinking the size of integrated circuits is commonly performed for all types of circuits as processing techniques improve over time to permit implementing smaller feature sizes. But there are usually limits of how far a given circuit layout can be shrunk in this manner, since there is often at least one feature that is limited as to how much, it can be shrunk. When this happens, designers will turn to a new or different layout or architecture of the circuit being implemented in order to reduce the amount of silicon area required to perform its functions. The shrinking of the above-described flash EEPROM integrated circuit systems can reach such limits.
One way to form small cells is to use a self-aligned Shallow Trench Isolation (STI) technique. This uses STI structures to isolate adjacent strings of floating gate cells such as those of NAND type memory arrays. According to this technique, a gate dielectric (tunnel dielectric) layer and floating gate polysilicon layer are formed first. Next, STI structures are formed by etching the gate dielectric and floating gate polysilicon layers and the underlying substrate to form trenches. These trenches are then filled with a suitable material (such as oxide) to form STI structures. The portions of the gate dielectric and floating gate polysilicon layers between STI structures are defined by the STI structures and are therefore considered to be self-aligned to the STI structures. Typically, the STI structures have a width that is equal to the minimum feature size that can be produced with the processing technology used. STI structures are also generally spaced apart by the minimum feature size. Thus, the portions of the gate dielectric and floating gate polysilicon layers between STI regions may also have a width that is equal to the minimum feature size. The strips of floating gate polysilicon are further formed into individual floating gates in later steps. In some examples, floating gates may have dimensions less than the minimum feature size that can be produced using photolithographic patterning alone. Examples of scheme for forming such floating gates are provided in U.S. Pat. No. 6,888,755.
In NAND and other types of nonvolatile memories, the amount of field coupling between floating gates and the control gates passing over them (the coupling ratio) is carefully controlled. The amount of coupling determines how much of a voltage that is placed on the control gate is coupled to the underlying floating gates. The percentage coupling is determined by a number of factors including the amount of surface area of the floating gate that overlaps a surface of the control gate. It is often desired to maximize the percentage coupling between the floating and control gates by maximizing the amount of overlapping area. One approach to increasing coupling area is described by Yuan et al in U.S. Pat. No. 5,343,063. The approach described in that patent is to make the floating gates thicker than usual to provide large vertical surfaces that may be coupled with the control gates.
Individual portions of a memory array, such as strings of a NAND array, are generally connected together using conductive lines that extend across the memory array. Some conductive lines may be connected to portions of the substrate so that electrical connections are made to those portions. Generally, such connections are made by forming an opening in a dielectric layer that overlies the substrate and forming a conductive plug by filling the opening with a conductive material such as a metal or doped polysilicon. As memories shrink, the lateral dimensions of such plugs generally shrink along with other memory features. However, the vertical dimensions of such plugs may not shrink in proportion. This may be because the thickness of floating gates remains high, or for other reasons.
The aspect ratio of an opening is the ratio of the height of the opening to a lateral dimension. FIG. 1 shows an opening 101 in a dielectric layer 103 on a substrate 105, opening 103 having a lateral dimension (width) of X1 and a height of Y1. The aspect ratio of opening 101 is Y1/X1. In general, as memories shrink, the aspect ratios of the openings used to form contacts to the underlying substrate increase because the vertical dimensions are not reduced in proportion to the lateral dimensions. In some newer devices the width of an opening used to form a contact may be 70 nanometers or less. The thickness of the dielectric layer may be 3000 Angstroms (300 nanometers) or more.
Increasing aspect ratios present certain problems in forming good quality contacts. Plugs are generally made by depositing a conductive material so that the material fills an opening. However, where openings have high aspect ratios, the deposited material may not fill an opening fully. In some cases, voids are formed in the conductive material deposited in an opening. FIG. 2 shows an example of an opening having an aspect ratio of Y2/X2 that has conductive material deposited in it to form a plug 210. However, within plug 210, a void 212 is formed because of the depth of the opening. Deposition near the top of the opening closes the opening before the lower part is completely filled so that void 212 is incorporated in plug 210. Such voids may cause device failure by increasing the electrical resistance of the plug, preventing current flow and causing heating. Some materials have good filling characteristics that allow good quality plugs to be formed even in openings having high aspect ratios. However, some of the materials that allow void-free plugs have relatively high resistivity so that the resistance of the plug is increased, which is undesirable. Certain formation techniques also have better filling characteristics than others.
Thus, there is a need for a method of forming a conductive plug in a manner that allows void-free plug formation even with high aspect ratio openings. There is also a need for a method of forming such a plug so that it has a low overall resistance. There is also a need for a method of forming such contacts in an efficient manner as part of memory array formation. There is also a need for void-free plugs with low resistance and for memory arrays having such void-free, low resistance plugs.